1. Field of the Invention
The present invention relates generally to the field of semiconductor chip processing, and more particularly, to the processing for an interlayer dielectric.
2. Description of the Related Art
Fluorinated SiO2 (typically PECVD or HDP) can be used to lower the dielectric constant of SiO2 from, for example, 4.0 to 3.6-3.8. The lowering of the dielectric constant is advantageous for a number of reasons, including to reduce the capacitance of the semiconductor device and thereby increase its performance.
However, fluorine in SiO2 will react with PVD barrier metals (Ti, TiN, Ta, TaN, Al, Cu, etc.) which are subsequently deposited on the surface of the fluorinated SiO2. This reaction between fluorine and the barrier metals will cause delamination on flat SiOF surfaces, as well as inside via holes.
Briefly, the present invention comprises, in one aspect, a method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF; and depleting the fluorine from a surface of the SiOF layer.
In a further aspect of this inventive method, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen to yield a treated surface.
In a yet further aspect of the present invention, the method comprises the step of passivating the treated surface.
In a further aspect of the present invention, the passivating step comprises the step of applying substantially pure nitrogen plasma to the treated surface.
In a yet further aspect of the present invention, the nitrogen plasma is applied at a lower plasma bias power and a higher pressure than the hydrogen-containing plasma used in the treating step.
In a further aspect of the present invention, the treating step is carried out in a CVD deposition chamber.
In a yet further aspect of the present invention, the depleting step forms a depletion layer that is greater Man or equal to 30 Angstroms in thickness.
In a further aspect of the present invention, the passivating step comprises the step of forming a passivation layer that is less than or equal to 25 Angstroms in thickness.
In a further embodiment of the present invention, a method is provided for using low dielectric SiOF in a process to manufacture semiconductor integrated circuit chips, comprising the steps of: obtaining a layer of SiOF; treating in a CVD-TiN deposition chamber a surface of the layer of SiOF with a plasma containing hydrogen to deplete fluorine from the surface; passivating the treated surface with substantially pure N2 plasma; and depositing a layer of TiN.
In a yet further embodiment of the present invention, a semiconductor chip is provided comprising: an integrated circuit with at least a first and second layers, and with a dielectric layer of SiOF disposed between said two layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
In a further aspect of this inventive embodiment, the predetermined depth of the first region is greater than or equal to 30 Angstroms.
In yet a further aspect of the present invention, the depth of the second region is less than or equal to 25 Angstroms.